The process of scaling integrated circuit (IC) chips has become more challenging as the feature size has been pushed into nanometer-technology nodes. In order to extend the scaling, engineers and scientists have attempted to not only shrink the feature size in x and y directions but also push IC devices into the third dimension. This book discusses the advantages of 3D devices and their applications in dynamic random access memory (DRAM), 3D-NAND flash, and advanced-technology-node CMOS ICs. Topics include the development of DRAM cell transistors and storage node capacitors; the manufacturing process of advanced buried-word-line DRAM; 3D FinFET CMOS IC devices; scaling trends of CMOS logic; devices that may be used in the "post-CMOS" era; and 3D technologies, such as the 3D-wafer process integration of silicon-on-ILD and TSV-based 3D packaging.
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